An interconnect (Vertical Interconnect Access) provides for an electrical connection between different layers of one or more semiconductor circuits. As one example, in the field of circuit/chip packaging, the demand for increasing device performance and flexibility requires increasing integration density. Three-dimensional (3D) integration techniques such as 3D-stacking can be employed, which includes vertical interconnection of chips and circuits by interconnects.
For silicon substrates, differences in CTE (Coefficient of Thermal Expansion) between the substrate and a component of the interconnect or TSV (Through-Silicon Interconnect), for example a metal component such as a metallization or metal core, can lead to mechanical stress at certain temperature regimes, e.g., during an operation. For other substrates, similar problems can occur. For example, copper filled TSVs exhibit a severe mismatch in CTE between the silicon substrate (CTE˜3 ppm/° C.) and the copper metal core (CTE˜17 ppm/° C.). At normal operation temperatures of semiconductor devices, typically <150° C., this results in a tensile mechanical stress in the silicon substrate in the near vicinity of the TSVs.
The stress may lead to changes in parameters of semiconductor circuit elements. For example, for a transistor element, parameters such as mobility, Vth, Idsat, etc. may be influenced. Considerable parameter changes can occur, for example, for FET (Field Effect Transistor) elements such as PFETs (p-type FETs) and NFETs (n-type FETs), and can be critical in particular for elements such as PMOSFETs, analog transistors, analog circuits, etc. These stress induced parameter changes may vary depending on the orientation of the transistor gates relative to the TSVs and also on the transistor architecture. For example, traditional planar transistors may be differently affected compared to new advanced multi-gate transistors, like Fin-FETs or Tri-Gate Transistors.
To minimize these effects of an interconnect, a Keep-Out Zone (KOZ) is defined on the substrate surface which is devoid of any circuit elements, such as transistors, which could be negatively influenced by the interconnect. As an example, for a TSV with a diameter of about 5 micrometer (μm), a KOZ of between 1 μm to 20 μm may be defined for digital FETs and a KOZ of between 20 μm to 200 μm may be defined for analog FETs. In general, size and extension of a KOZ may depend, for example, on number, sizes and layouts of a single interconnect, multiple interconnects, arrays or matrices of interconnects, etc.
As is clear from the above number values, a KOZ can have a considerable impact on circuit layout, chip design, etc., as it can lead to a considerable loss of substrate area, with corresponding increases of costs for devices such as, for example, 3D-stacked chip assemblies. Therefore there is a general need for cost-efficient design and manufacture approaches for semiconductor devices including interconnects.